custom-nas/electrical/05_KiCad8_Signal_Integrity_and_PCB_Design_Rules.md

KiCad 8 Signal Integrity & 4-Layer FR4 Substrate Routing Rules

System: 6U 19-Inch Open-Source Tri-Mode Storage Array
Document ID: ELEC-SPEC-05
Target PCB Stack-Up: JLC04161H-7628 (Standard 4-Layer FR4, 1.6mm Finished Thickness)
EDA Software: KiCad 8.0+ (with Custom Design Rule Checker .kicad_dru)

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1. 4-Layer FR4 Physical Stack-Up Specifications

                     4-LAYER CONTROLLED IMPEDANCE STACK-UP
                     
  Layer 1 (Top):     0.035mm Finished Copper (1.0 oz) ──► PCIe & SAS Microstrip Lines
  ─────────────────  ─────────────────────────────────────────────────────────────────
  Prepreg 7628:      0.2104mm (8.28 mils), Dielectric Constant ε_r = 4.3 @ 5 GHz
  ─────────────────  ─────────────────────────────────────────────────────────────────
  Layer 2 (Inner 1): 0.0175mm Solid Copper (0.5 oz)   ──► Continuous Solid GND Plane
  ─────────────────  ─────────────────────────────────────────────────────────────────
  FR4 Core:          1.0650mm (41.93 mils), ε_r = 4.5
  ─────────────────  ─────────────────────────────────────────────────────────────────
  Layer 3 (Inner 2): 0.0175mm Split Copper (0.5 oz)   ──► 12V, 5V, 3.3V Power Planes
  ─────────────────  ─────────────────────────────────────────────────────────────────
  Prepreg 7628:      0.2104mm (8.28 mils), ε_r = 4.3 @ 5 GHz
  ─────────────────  ─────────────────────────────────────────────────────────────────
  Layer 4 (Bottom):  0.035mm Finished Copper (1.0 oz) ──► Low-Speed Signals & Passives

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2. Microstrip Controlled Differential Impedance Geometries

Using 2D boundary element electromagnetic field solvers configured for the JLC04161H-7628 stack-up parameters:

High-Speed Protocol	Differential Target (Z_{\text{diff}})	Trace Width (W)	Differential Gap (S)	Single-Ended Imp. (Z_0)	Loss @ 6 GHz (FR4)
PCI Express Gen 3.0	\mathbf{85.0\,\Omega \pm 10\%}	0.230\,\text{mm} (9.0 mil)	0.150\,\text{mm} (6.0 mil)	52.8\,\Omega	0.85\,\text{dB/inch}
SAS-3 (12.0 Gbps)	\mathbf{100.0\,\Omega \pm 10\%}	0.180\,\text{mm} (7.0 mil)	0.230\,\text{mm} (9.0 mil)	59.4\,\Omega	1.15\,\text{dB/inch}
100MHz HCSL Clock	\mathbf{85.0\,\Omega \pm 10\%}	0.230\,\text{mm} (9.0 mil)	0.150\,\text{mm} (6.0 mil)	52.8\,\Omega	0.35\,\text{dB/inch}

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3. High-Speed Routing Constraints & Clearance Matrix

                      DIFFERENTIAL PAIR GEOMETRY & CLEARANCE
                      
                      │◄─ W ─►│◄─ S ─►│◄─ W ─►│
                      ┌───────┐       ┌───────┐
                      │  P+   │       │  N-   │  ▲
                      └───────┘       └───────┘  │ H = 0.2104mm (Prepreg)
             ═══════════════════════════════════ ▼ ═════════════════════
             ▓▓▓▓▓▓▓▓ Layer 2: Solid Contiguous GND Reference ▓▓▓▓▓▓▓▓▓▓
             
             ◄─────────────── 5W Inter-Pair Spacing ───────────────────►

3.1 Strict Design Rules:

1. Intra-Pair Skew (Length Matching):
   • PCIe Gen 3 differential pairs (TX_P/TX_N and RX_P/RX_N): Matched within \Delta L \le 0.127\,\text{mm} (5.0\,\text{mils}).
   • Broadcom SerDes SAS 12G differential pairs: Matched within \Delta L \le 0.050\,\text{mm} (2.0\,\text{mils}).
   • Skew compensation serpentines must be inserted immediately at the point of discrepancy (e.g., inside BGA escape turns).
2. Inter-Pair Spacing (5\times W Rule):
   • The edge-to-edge gap between adjacent differential pairs must be \ge 5\times W = \mathbf{1.15\,\text{mm}} (45.0\,\text{mils}) to guarantee Near-End Crosstalk (NEXT) isolation > -40\,\text{dB}.
3. Glass-Weave Fiber Skew Mitigation:
   • Because standard FR4 7628 prepreg uses woven fiberglass bundles with a higher dielectric constant (\epsilon_{r,\text{glass}} \approx 6.0) than the surrounding epoxy resin (\epsilon_{r,\text{resin}} \approx 3.4), routing differential pairs parallel to the X or Y axis causes differential phase velocity mismatches.
   • Mandate: All high-speed SerDes and PCIe tracks in KiCad must be routed at a 12.5^\circ to 15.0^\circ angle relative to the board edges.
4. Via Antipad & Ground Return Stitching:
   • Signal Via Geometry: Drill = 0.25\,\text{mm} (10\,\text{mil}), Pad Diameter = 0.50\,\text{mm} (20\,\text{mil}).
   • Layer 2 & Layer 3 Antipad Void: Diameter = \mathbf{0.80\,\text{mm}} (32\,\text{mil}) to cancel parasitic via capacitance.
   • GND Return Vias: Exactly two GND stitching vias must be placed within $0.40,\text{mm}$ of every signal via transition pair to provide an immediate, low-inductance return path.