143 lines
11 KiB
Markdown
143 lines
11 KiB
Markdown
# Master Engineering Specification & Architecture Baseline: Open-Source 6U 19-Inch Tri-Mode Storage Array
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**Document Version:** 1.0
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**Target Environment:** Open-Source Hardware / KiCad 8 / EIA-310-D 19-Inch 6U Rackmount
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**Author:** Hardware Engineering Architecture Team
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---
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## 1. Executive Summary & Design Philosophy
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This document serves as the authoritative baseline specification for an open-source, enterprise-capable **6U 19-inch rackmount hybrid storage array**. The architecture is engineered to challenge expensive, proprietary Storage Area Networks (SANs) by pairing democratized compute silicon, enterprise-grade storage controllers, and low-cost manufacturing methods.
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### Core Strategic Targets:
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- **Bill of Materials (BOM) Target:** Carrier Baseboard + Compute Engine < **$100** (est. $92.50); Mechanical Skeleton & Facade < **$65** (est. $61.50). Total core unit target: **~$155–$175**.
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- **Universal Storage Protocol Compatibility:** Native support for **SAS (12Gb/s)**, **SATA (6Gb/s)**, and **PCIe NVMe (U.2/U.3 SFF-TA-1001)** within the same physical bays without converter adapters.
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- **Manufacturing Democratization:** 4-layer standard FR4 PCB substrate, 2020 T-slot aluminum extrusion internal frame, and modular interlocking 3D-printed facade parts sized for standard desktop 3D printers ($\le 220\,\text{mm} \times 220\,\text{mm}$ build plates).
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- **Rail-Less Mounting:** Uses heavy-gauge steel rack ears and static 4-post shelves/L-runners (or OCP OrV3 sled mounting) to eliminate expensive, finicky telescoping server rails.
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---
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## 2. System Architecture & Silicon Selection
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```
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+-----------------------------------------------------------------------------------+
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| 6U CHASSIS ENVELOPE |
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| |
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| +------------------------+ +---------------------+ +----------------+ |
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| | Radxa CM3 (RK3568) | | Broadcom Tri-Mode | | 8x U.3 Drives | |
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| | - Quad Cortex-A55 | PCIe | SAS3408 / SAS3416 | MCIO | (NVMe/SAS/SATA)| |
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| | - 1 TOPS NPU | Gen3 | - Dual Cortex-A15 |=====>| - Hot-Swap Sled| |
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| | - 4GB/8GB LPDDR4 | x2 | - Tri-Mode SerDes | Twin | - SFF-TA-1001 | |
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| | - Dual GbE NICs |=====>| - DataBolt Aggreg. | Ax | Universal Bay| |
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| +-----------+------------+ +----------+----------+ +----------------+ |
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| | UART/I2C | Sideband/SGPIO |
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| v v |
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| +-----------------------------------------------------+ |
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| | Raspberry Pi RP2040 Auxiliary Management MCU | |
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| | - Staggered Spin-Up (PUIS) Power Sequencing | |
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| | - 4-Pin PWM Closed-Loop Thermal PID Fan Control | |
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| | - Multi-Point I2C Environmental Telemetry | |
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| +-----------------------------------------------------+ |
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+-----------------------------------------------------------------------------------+
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```
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### 2.1 Compute Subsystem: Radxa Compute Module 3 (RK3568)
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- **SoC:** Rockchip RK3568 (Quad-core ARM Cortex-A55 @ 2.0 GHz, 64-bit).
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- **AI Acceleration:** Integrated 1.0 TOPS NPU utilized for on-device S.M.A.R.T. telemetry analysis, predictive drive degradation heuristics, and automated caching tier algorithms.
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- **Memory:** 4GB to 8GB LPDDR4 @ 3200 MT/s (sufficient for Linux OS and ZFS ARC metadata caching).
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- **I/O Topology:**
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- 1x PCIe Gen 3.0 (x2 lanes, 16 Gbps raw / ~1.97 GB/s theoretical) dedicated as the upstream host link to the storage controller.
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- 1x PCIe Gen 2.0 (1 lane) available for auxiliary 2.5GbE/10GbE network expansion.
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- Dual GbE interfaces directly exposed.
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- **Idle Power:** $\le 2.0\,\text{W}$ system idle.
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### 2.2 Storage Controller Silicon: Broadcom SAS3408 / SAS3416
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- **Architecture:** 6th Generation Tri-Mode I/O Controller (IOC) featuring embedded dual-core ARM Cortex-A15 @ 1.2 GHz.
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- **Performance:** >1,000,000 IOPS; manages up to 2,000 devices via Fusion-MPT architecture without requiring dedicated controller DDR RAM.
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- **Tri-Mode SerDes:** Hardware auto-negotiation per PHY between SAS 12G/6G/3G, SATA 6G/3G, and PCIe NVMe 8GT/s (Gen 3).
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- **DataBolt™ Technology:** Buffers and aggregates 6Gb/s SATA/SAS data streams into full 12Gb/s fabric bandwidth to prevent slow disks from bottlenecking high-speed channels.
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### 2.3 Auxiliary Management Microcontroller: Raspberry Pi RP2040
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- **Role:** OpenBMC-lite physical layer supervisor running deterministic C/C++ firmware.
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- **Responsibilities:**
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1. **Power-Up In Standby (PUIS) & Staggered Spin-up:** Sequences drive spin-up via SAS/SATA Pin 11 to avoid inrush current collapse on the 12V power rail.
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2. **Closed-Loop Thermal Management:** Reads multi-point I2C temperature sensors (TMP117 / MCP9808) placed across the drive bay, controller heatsink, and power stage; drives 4-pin PWM enterprise fan curves.
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3. **Host Interface:** Reports environmental metrics, fan RPMs, and rail voltages to the RK3568 host via UART/I2C.
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---
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## 3. High-Speed Interconnect & PCB Strategy
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### 3.1 4-Layer FR4 Baseboard Design (KiCad 8)
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- **Target Substrate:** Standard 4-layer FR4 (e.g., JLC04161H-7628 stack-up, 1.6mm thickness, 1 oz copper weight).
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- **Stack-Up:** L1 (High-Speed Signal / Components) - L2 (Solid GND Reference) - L3 (12V/5V/3.3V Power Planes) - L4 (Low-Speed Signal / Auxiliary Power).
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- **Controlled Impedance Targets:**
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- **PCIe Gen 3 Differential Pairs:** $85\,\Omega \pm 10\%$
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- **SAS 12G Differential Pairs:** $100\,\Omega \pm 10\%$
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- **Trace Length Mitigation:** High-speed traces on the FR4 board are strictly constrained to $\le 4\,\text{inches}$ (100 mm) between chip pins and connector pads.
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- **Cable Offloading Architecture:** High-speed SerDes lines are broken out immediately into high-density **SFF-TA-1016 (MCIO)** or **SlimSAS** surface-mount connectors. Inexpensive twinaxial copper ribbon cables transport signals directly to the backplane, eliminating the need for expensive 8–10 layer low-loss PCB substrates.
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---
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## 4. Power Delivery Network (PDN) & PLP Architecture
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### 4.1 Native 12V DC Decoupled Bus
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- **Main Power Bus:** 12V DC unified main rail fed by external mass-produced commodity power bricks.
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- **Input Interfaces:**
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- *Profile A (Drive-Only / Low-Wattage):* 12V 10A–15A (120W–180W) standard DC barrel jack.
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- *Profile B (GPU Growth / High-Wattage):* High-current Molex Mini-Fit Jr. 6-pin/8-pin receptacle (handles up to 300W–500W external supply).
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- **Front-End Protection:** Ideal Diode Controller IC (e.g., TI LM74700-Q1 or LTC4357) on the 12V input to protect against reverse polarity, overvoltage spikes, and back-feeding.
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- **Local Step-Down Regulation:** High-efficiency synchronous buck converters on the carrier PCB:
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- $12\,\text{V} \rightarrow 5.0\,\text{V} \ @ \ 10\,\text{A}$ (HDD logic boards & USB subsystem).
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- $12\,\text{V} \rightarrow 3.3\,\text{V} \ @ \ 5\,\text{A}$ (Radxa CM3, Broadcom IOC logic, RP2040, backplane sideband).
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### 4.2 Power Loss Protection (PLP) Circuit (Open Engineering Target)
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- **Goal:** Hardware supercapacitor (or tantalum polymer) energy storage bank that provides sufficient holdup time during sudden AC mains loss.
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- **Target Function:** Keep the 12V/5V/3.3V rails alive for $\sim 50\,\text{ms} - 250\,\text{ms}$ while asserting an emergency interrupt to the RK3568 and Broadcom IOC to flush in-flight volatile write caches to non-volatile media.
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---
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## 5. Mechanical Enclosure & Thermal Architecture
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```
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+-----------------------------------------------------------------------------------+
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| FRONT (Intake) REAR (Exhaust)|
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| [Modular 3D Facade] -> [8x 3.5"/U.3 Bays] -> [Fan Wall] -> [Open Mezzanine Area] |
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| (PETG/ASA Dovetails) (Front 4-5 inches) (3x 120mm) (10-14" GPU/Compute) |
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+-----------------------------------------------------------------------------------+
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```
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### 5.1 Hybrid Structural Skeleton
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- **Primary Frame:** 2020 (20mm x 20mm) T-slot / V-slot anodized aluminum extrusions.
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- **Outer Skin:** Flat 1.0mm–1.5mm galvanized steel or aluminum sheet metal panels (simple laser/waterjet cut rectangles, no complex stamping).
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- **Fastening System:** M3 and M4 drop-in extrusion T-nuts paired with heat-set brass threaded inserts in all plastic components (zero direct tapping into polymer).
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- **Rack Mounting:** Heavy-gauge 3mm steel 6U rack ears bolted directly into frame corners; slides onto static 4-post heavy-duty shelves or L-runners (bypassing telescoping rails).
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### 5.2 3D-Printable Facade & Modularity
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- **Material:** PETG, ABS, or ASA (PLA strictly forbidden due to thermal creep under 50°C+ ambient server loads).
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- **Print Bed Optimization:** Front facade split into 3–4 interlocking sections utilizing dovetail joints, allowing fabrication on standard 220mm desktop 3D printers.
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- **Internal Expansion:** Front 4–5 inches house the drive cage and carrier backplane; rear 10–14 inches provide an unobstructed vertical mezzanine compute area for full-height PCIe/GPU accelerator cards.
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---
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## 6. Open Technical Questions & Directives for Deep Research
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The following subsystems require exhaustive engineering research, mathematical validation, and component selection:
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1. **PLP Circuitry & Energy Calculations:**
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- Exact mathematical derivation of required capacitance $C = \frac{2 \cdot P \cdot t}{\eta \cdot (V_{\text{start}}^2 - V_{\text{drop}}^2)}$ for a 120W peak load with a 100ms holdup window.
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- Component selection (LTC3350, LTC4041, or TPS25982 eFuse) with exact Manufacturer Part Numbers (MPNs) and sub-$8 budget target.
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2. **High-Speed Pinout & Routing Specification:**
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- Complete pin-to-pin schematic mapping from Radxa CM3 (PCIe 3.0 x2) to Broadcom SAS3408/3416 host pins.
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- SFF-TA-1016 (MCIO) to U.3 (SFF-TA-1001) backplane SerDes breakout wiring table.
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- High-speed signal integrity layout rules in KiCad 8 (via stitching, antipad sizing, AC coupling cap placement).
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3. **RP2040 OpenBMC Firmware Architecture:**
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- State machine design for PUIS staggered spin-up delays (e.g., 2-second staggered spin interval per drive).
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- Closed-loop PID fan curve algorithm based on multi-zone I2C temperature inputs.
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- Host communication protocol specification (UART/I2C command structure).
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4. **Thermal CFD & Airflow Budgeting:**
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- Total CFM and static pressure ($\text{mm}\,\text{H}_2\text{O}$) required to pull air through dense 8-drive mechanical/NVMe arrays and cool high-power components.
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- Selection of 80mm / 120mm enterprise PWM fans with optimal acoustic and static pressure profiles.
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