# Passive 8-Bay U.3 (SFF-TA-1001) Backplane & PUIS Switching Schematic

**System:** 6U 19-Inch Open-Source Tri-Mode Storage Array  
**Document ID:** ELEC-SPEC-04  
**Connector Standard:** SFF-TA-1001 (U.3 Universal Drive Receptacle, SFF-8639 Body)  
**Drive Form Factor:** 8x 3.5" Enterprise SAS/SATA HDDs or 2.5" U.2/U.3 NVMe SSDs  
**Power-Up in Standby (PUIS):** Active N-Channel MOSFET Pin 11 Staggered Spin-Up Circuit  
**GPIO Controller:** Texas Instruments `TCA9539PWR` (16-bit I2C GPIO Expander, I2C Address `0x74`)  

---

## 1. Universal U.3 Dynamic Pin Multiplexing

The SFF-TA-1001 (U.3) standard collapses legacy SAS/SATA and PCIe NVMe cabling onto identical physical pins on the SFF-8639 connector body.

```
       SFF-TA-1001 (U.3) DYNAMIC PROTOCOL PIN RE-USE
       
       Pin Location    SATA Mode       SAS 12G Mode    NVMe (PCIe) Mode
       ─────────────────────────────────────────────────────────────────
       S2 / S3         SATA_RX_P/N     SAS_RX0_P/N     PCIe_Lane0_RX_P/N
       S5 / S6         SATA_TX_P/N     SAS_TX0_P/N     PCIe_Lane0_TX_P/N
       S9 / S10        NC / Ground     SAS_RX1_P/N     PCIe_Lane1_RX_P/N
       S12 / S13       NC / Ground     SAS_TX1_P/N     PCIe_Lane1_TX_P/N
       P11             Staggered Spin  Activity/PUIS   Activity / Alert LED
```

---

## 2. Pin 11 PUIS Staggered Spin-Up FET Switching Circuit

When 8 high-performance enterprise 7200 RPM drives power on simultaneously, mechanical spindle motor inrush current pulls over $24\,\text{A}$ ($288\,\text{W}$), collapsing a $120\text{W}$ power delivery rail.

To stagger drive spin-up, the backplane integrates an active low-side N-channel MOSFET switch on Pin 11 of each drive receptacle, controlled by the RP2040 OpenBMC microcontroller via an I2C GPIO expander.

```
                  PIN 11 PUIS SWITCH PER DRIVE BAY (BAY 0 to 7)
                  
                                           +3.3V_AUX
                                               │
                                            [10kΩ] (R_pullup)
                                               │
                                               ├────────► To SFF-8639 Pin 11 (P11)
                                               │
                                             D ┌──┐
    RP2040 GPIO / TCA9539 (PUIS_EN_BAYx) ────►G┤  │ Q_puis (2N7002 / BSS138)
    - Logic 0 (0V): Spindle Dormant (PUIS)   S └──┘
    - Logic 1 (3.3V): Spindle Accelerates      │
                                              GND
```

### 2.1 Component Specifications (Per Bay $\times 8$)
| RefDes (Bay 0) | Component Description | Manufacturer & MPN | Specifications |
| :--- | :--- | :--- | :--- |
| **$Q_{301}$** | Low-Side N-Channel MOSFET | ON Semi `2N7002K` / `BSS138` | 60V, 300mA, $V_{GS(\text{th})} = 1.6\,\text{V}$, SOT-23 |
| **$R_{301}$** | Pin 11 Pull-Up Resistor | Yageo `RC0402FR-0710KL` | $10.0\,\text{k}\Omega \pm 1\%$, 0402 Thick Film |
| **$R_{302}$** | Gate Series Damping Resistor | Yageo `RC0402FR-07100RL` | $100\,\Omega \pm 1\%$, 0402 (prevents gate ringing) |
| **$D_{301}$** | Activity LED (Green / Amber) | Lite-On `LTST-C190KGKT` | 0603 SMD LED, driven by Pin 11 low state |

---

## 3. Backplane I2C GPIO Expander Subsystem

The 8-channel staggered spin-up gates are orchestrated by a single `TCA9539PWR` 16-bit I2C I/O expander located on the backplane, communicating with the baseboard RP2040 microcontroller over the MCIO sideband I2C bus (`I2C_UBM_SCL` / `I2C_UBM_SDA`).

| Expander Pin | Port Bit | Net Name | Target Drive Bay & Function |
| :---: | :---: | :--- | :--- |
| **Pin 4** | `P0_0` | `PUIS_GATE_BAY0` | Bay 0 Spindle Spin-Up Enable Gate |
| **Pin 5** | `P0_1` | `PUIS_GATE_BAY1` | Bay 1 Spindle Spin-Up Enable Gate |
| **Pin 6** | `P0_2` | `PUIS_GATE_BAY2` | Bay 2 Spindle Spin-Up Enable Gate |
| **Pin 7** | `P0_3` | `PUIS_GATE_BAY3` | Bay 3 Spindle Spin-Up Enable Gate |
| **Pin 8** | `P0_4` | `PUIS_GATE_BAY4` | Bay 4 Spindle Spin-Up Enable Gate |
| **Pin 9** | `P0_5` | `PUIS_GATE_BAY5` | Bay 5 Spindle Spin-Up Enable Gate |
| **Pin 10**| `P0_6` | `PUIS_GATE_BAY6` | Bay 6 Spindle Spin-Up Enable Gate |
| **Pin 11**| `P0_7` | `PUIS_GATE_BAY7` | Bay 7 Spindle Spin-Up Enable Gate |
| **Pin 13**| `P1_0` | `PRSNT_BAY0#` | Bay 0 Drive Hardware Presence Detect (Input) |
| **Pin 14**| `P1_1` | `PRSNT_BAY1#` | Bay 1 Drive Hardware Presence Detect (Input) |
| **Pin 15**| `P1_2` | `PRSNT_BAY2#` | Bay 2 Drive Hardware Presence Detect (Input) |
| **Pin 16**| `P1_3` | `PRSNT_BAY3#` | Bay 3 Drive Hardware Presence Detect (Input) |
| **Pin 17**| `P1_4` | `PRSNT_BAY4#` | Bay 4 Drive Hardware Presence Detect (Input) |
| **Pin 18**| `P1_5` | `PRSNT_BAY5#` | Bay 5 Drive Hardware Presence Detect (Input) |
| **Pin 19**| `P1_6` | `PRSNT_BAY6#` | Bay 6 Drive Hardware Presence Detect (Input) |
| **Pin 20**| `P1_7` | `PRSNT_BAY7#` | Bay 7 Drive Hardware Presence Detect (Input) |

---

## 4. Backplane Power Plane & Decoupling Network

To eliminate high-frequency ripple and prevent localized ground bounce during drive writes:

1. **Power Copper Pour Layering (4-Layer Backplane):**
   - **Layer 1 (Top):** SFF-8639 Surface Mount Pads & SerDes Escape Traces.
   - **Layer 2 (Inner 1):** Solid Contiguous Ground (`GND`) Plane (2.0 oz finished copper).
   - **Layer 3 (Inner 2):** Split Power Plane (+12V Bus Copper Zone + +5V Bus Copper Zone, 2.0 oz copper).
   - **Layer 4 (Bottom):** Low-speed I2C/PUIS routing and thermal dissipation pours.
2. **Per-Bay Decoupling Capacitor Array:**
   - **+12V Rail (Pins P13, P14, P15):** $1\times 22\,\mu\text{F}$ 25V 1210 X7R ceramic + $2\times 0.1\,\mu\text{F}$ 50V 0402 ceramic placed $< 2.0\,\text{mm}$ from connector power pins.
   - **+5V Rail (Pins P7, P8, P9):** $1\times 22\,\mu\text{F}$ 10V 1206 X7R ceramic + $2\times 0.1\,\mu\text{F}$ 16V 0402 ceramic.
   - **+3.3V Pre-charge (Pins P1, P2, P3):** $1\times 4.7\,\mu\text{F}$ 0805 + $1\times 0.1\,\mu\text{F}$ 0402 ceramic.