# Radxa CM3 (RK3568) to Broadcom SAS3408/SAS3416 PCIe Interconnect Netlist **System:** 6U 19-Inch Open-Source Tri-Mode Storage Array **Document ID:** ELEC-SPEC-02 **Host Controller:** Radxa Compute Module 3 (Rockchip RK3568 SoC) **Endpoint Silicon:** Broadcom SAS3408 / SAS3416 6th-Gen Tri-Mode IOC **Bus Protocol:** PCI Express Base Specification Revision 3.1 (8.0 GT/s, x2 Link Width) **AC Coupling:** 100nF 0402 X7R $\pm 10\%$ Ceramic (50V Rating, C0G/X7R Dielectric) --- ## 1. High-Speed Differential Pair Netlist Because PCI Express utilizes Current Mode Logic (CML) differential drivers with disparate internal common-mode DC biasing between the Rockchip SoC and Broadcom silicon, series DC blocking (AC coupling) capacitors are mandatory on all Transmit ($TX$) differential lines. ``` PCIE GEN 3.0 x2 INTERCONNECT TOPOLOGY [Radxa CM3 Host (RK3568)] [Broadcom SAS3408 Endpoint] PCIE30_TX0_P ──[ 100nF 0402 ]────────────────────────► PET0_P (Host RX0+) PCIE30_TX0_N ──[ 100nF 0402 ]────────────────────────► PET0_N (Host RX0-) PCIE30_RX0_P ◄────────────────────────[ 100nF 0402 ]── PER0_P (Host TX0+) PCIE30_RX0_N ◄────────────────────────[ 100nF 0402 ]── PER0_N (Host TX0-) PCIE30_TX1_P ──[ 100nF 0402 ]────────────────────────► PET1_P (Host RX1+) PCIE30_TX1_N ──[ 100nF 0402 ]────────────────────────► PET1_N (Host RX1-) PCIE30_RX1_P ◄────────────────────────[ 100nF 0402 ]── PER1_P (Host TX1+) PCIE30_RX1_N ◄────────────────────────[ 100nF 0402 ]── PER1_N (Host TX1-) PCIE_REFCLK_P ───────────────────────────────────────► REFCLK_P (100 MHz) PCIE_REFCLK_N ───────────────────────────────────────► REFCLK_N (100 MHz) ``` --- ## 2. Complete Pin-to-Pin Schematic Netlist Mapping | Net Name | Radxa CM3I Pin (100-Pin B2B) | AC Coupling Spec & Placement | Broadcom SAS3408 Pin (BGA-484) | Signal Description & Protocol | | :--- | :---: | :--- | :---: | :--- | | **PCIE_TX0_P** | Pin 42 (`PCIE30_TX0_P`) | $C_{101}$: 100nF 0402, placed $< 5\text{mm}$ from CM3 | Pin E12 (`PET0_P`) | Host Data Lane 0 Transmit (+) | | **PCIE_TX0_N** | Pin 44 (`PCIE30_TX0_N`) | $C_{102}$: 100nF 0402, placed $< 5\text{mm}$ from CM3 | Pin E13 (`PET0_N`) | Host Data Lane 0 Transmit (-) | | **PCIE_RX0_P** | Pin 48 (`PCIE30_RX0_P`) | $C_{103}$: 100nF 0402, placed $< 5\text{mm}$ from Broadcom | Pin F14 (`PER0_P`) | Host Data Lane 0 Receive (+) | | **PCIE_RX0_N** | Pin 50 (`PCIE30_RX0_N`) | $C_{104}$: 100nF 0402, placed $< 5\text{mm}$ from Broadcom | Pin F15 (`PER0_N`) | Host Data Lane 0 Receive (-) | | **PCIE_TX1_P** | Pin 54 (`PCIE30_TX1_P`) | $C_{105}$: 100nF 0402, placed $< 5\text{mm}$ from CM3 | Pin G12 (`PET1_P`) | Host Data Lane 1 Transmit (+) | | **PCIE_TX1_N** | Pin 56 (`PCIE30_TX1_N`) | $C_{106}$: 100nF 0402, placed $< 5\text{mm}$ from CM3 | Pin G13 (`PET1_N`) | Host Data Lane 1 Transmit (-) | | **PCIE_RX1_P** | Pin 60 (`PCIE30_RX1_P`) | $C_{107}$: 100nF 0402, placed $< 5\text{mm}$ from Broadcom | Pin H14 (`PER1_P`) | Host Data Lane 1 Receive (+) | | **PCIE_RX1_N** | Pin 62 (`PCIE30_RX1_N`) | $C_{108}$: 100nF 0402, placed $< 5\text{mm}$ from Broadcom | Pin H15 (`PER1_N`) | Host Data Lane 1 Receive (-) | | **PCIE_CLK_P** | Pin 34 (`PCIE_REFCLK_P`)| Direct DC Coupled (0Ω jumper / direct trace) | Pin C10 (`REFCLK_P`) | 100 MHz HCSL Differential Clock (+) | | **PCIE_CLK_N** | Pin 36 (`PCIE_REFCLK_N`)| Direct DC Coupled (0Ω jumper / direct trace) | Pin C11 (`REFCLK_N`) | 100 MHz HCSL Differential Clock (-) | | **PCIE_PERST#**| Pin 30 (`GPIO3_D0`) | Direct 3.3V LVCMOS trace | Pin B8 (`PERST#`) | System Reset (Active Low) | | **PCIE_WAKE#** | Pin 32 (`GPIO3_D1`) | $10\,\text{k}\Omega$ pull-up to +3.3V ($R_{101}$) | Pin B9 (`WAKE#`) | PCIe Wake Event (Open Drain) | | **PCIE_CLKREQ#**| Pin 28 (`GPIO3_C7`) | $10\,\text{k}\Omega$ pull-up to +3.3V ($R_{102}$) | Pin A8 (`CLKREQ#`)| Clock Request (Power Management) | --- ## 3. Unused Broadcom PCIe Host Lanes Termination The Broadcom SAS3408/SAS3416 silicon provides an x8 host link. Because the RK3568 host operates at x2 link width, the controller automatically negotiates down to an x2 logical link during Link Training and Status State Machine (LTSSM) initialization. To prevent floating gate oxide stress and reduce static leakage power: - **Unused Transmit Pins (Lanes 2 through 7: `PET2_P/N` to `PET7_P/N`):** Leave as No Connect (`NC`). The Broadcom CML output stages high-impedance tri-state unused drivers automatically. - **Unused Receive Pins (Lanes 2 through 7: `PER2_P/N` to `PER7_P/N`):** Terminate to board Ground (`GND`) through $1.0\,\text{k}\Omega$ pull-down resistors (or direct AC ground coupling through 100nF caps) per Broadcom Hardware Design Guide Section 4.2. --- ## 4. Sideband Management & SGPIO / UBM Routing To enable seamless drive status monitoring, activity flashing, and enclosure telemetry: ``` [Radxa CM3 (RK3568)] ◄── I2C Bus 3 (400 kHz) ──► [Broadcom SAS3408] - /dev/i2c-3 master controller - UBM (Universal Backplane Mgmt) [Broadcom SAS3408] ─── SGPIO Bus (SFF-8485) ───► [Passive U.3 Backplane] - SCLOCK (Shift Clock) - Backplane CPLD / Shift Regs - SLOAD (Frame Load) - Drive Activity & Fault LEDs - SDATAOUT (Transmit State) - SDATAIN (Receive State) ``` | Sideband Net Name | Source Pin (SAS3408) | Target Pin (MCIO Sideband / Backplane) | Protocol / Function | | :--- | :---: | :---: | :--- | | **SGPIO_SCLK** | Pin AA14 | MCIO 8i Sideband Pin A12 | SGPIO Serial Clock (up to 20 MHz) | | **SGPIO_SLOAD** | Pin AA15 | MCIO 8i Sideband Pin A13 | SGPIO Frame Synchronization / Latch | | **SGPIO_SDOUT** | Pin AB14 | MCIO 8i Sideband Pin A14 | SGPIO Transmit Data (LED Drive Patterns) | | **SGPIO_SDIN** | Pin AB15 | MCIO 8i Sideband Pin A15 | SGPIO Receive Data (Drive Presence Detect) | | **I2C_UBM_SCL** | Pin AC10 | MCIO 8i Sideband Pin B12 | Universal Backplane Management Clock | | **I2C_UBM_SDA** | Pin AC11 | MCIO 8i Sideband Pin B13 | Universal Backplane Management Data |